Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36. Word line leakage current through support pillar structures in contact regions results in degradation in device performance. Such leakage current can be caused by damages to dummy memory films produced by reaction ion etch processes that are employed during formation of memory stack structures. In addition, insufficient mechanical strength in the support pillar structures can cause various structural deformations during processing steps. Thus, improved support pillar structures are desired which can provide reduced word line leakage current and sufficient structure strength.